Recently, a flat panel display, such as a liquid crystal display, has become popular. FIG. 22 shows a general configuration of a data driver for outputting a level voltage to a data line of a display unit based on video signal. Referring to FIG. 22, this data driver at least includes a grayscale voltage generating circuit 920, a plural number of decoders 930 (selection circuits), and a plural number of buffer circuits 910. The grayscale voltage generating circuit 920 is formed by a resistor string, connected between a power supply VA and another power supply VB, and outputs a plural number of grayscale voltages, corresponding to the number of the grayscales, from respective terminals (taps) of the resistor string. Each decoders 930 is supplied with the grayscale voltages and a digital video signal and selects the grayscale voltage associated with the digital video signal to output the so selected grayscale voltage to the buffer circuit 910. Each buffer circuit 910 current-amplifies the grayscale voltage for outputting to an output terminal. The decoders 930 and the buffer circuits 910 are provided for the respective outputs and the grayscale voltage generating circuit 920 is co-owned by all of these outputs. The video signal supplied to the decoder 930 are digital video signal processed e.g. by a data register, a latch or by a level shifter, not shown.
Since it is requested for the data driver to output the grayscale voltages free of variations to a number of data lines, high output voltage accuracy is required of the buffer circuits 910. For the buffer circuits, the configuration shown for example in FIGS. 23 and 25 has been proposed (see Patent Publications 1 and 2, indicated below).
The differential amplifier circuit, shown in FIG. 23, is an offset canceling amplifier, having the function of suppressing the output offset ascribable to variations in transistor devices making up the circuit. FIG. 23 shows the configuration disclosed in the Patent Publication 1 as later explained, and FIG. 24 is a timing diagram showing the switch on/off of the circuit of FIG. 23.
Referring to a timing chart of FIG. 24, in a circuit shown in FIG. 23, switches SW1 and SW3 are turned on, whilst a switch SW2 is turned off, during a time period t1 of one data output period. An input voltage Vin and an output voltage Vout are supplied to an input pair of a differential pair (M3, M4). The input voltage Vin is also supplied to another input pair of a differential pair (M5, M6). At this time, the output voltage Vout is a voltage including an offset voltage Vf (Vin+Vf), this voltage Vf being stored in a capacitor C1.
Then, during the time period t2, the switches SW1 and SW3 are turned off, whilst the switch SW2 is turned on. The input voltage Vin and a voltage stored in the capacitor C1 (Vin+Vf) are supplied to the input pair of the differential pair (M3, M4), whilst the input voltage Vin and the output voltage Vout are supplied to the input pair of the differential pair (M5, M6).
At this time, the same voltage as that during the time period t1 is supplied to the input pair of the differential pair (M3, M4) to maintain the differential pair (M5, M6) in the same state as that during the time period t1. Consequently, the output voltage Vout during the time period t2 is equal to the input voltage Vin and remains stable. Thus, in the circuit configuration, shown in FIG. 23, the output offset may be canceled, so that a voltage equal to the input voltage may be amplified to output the so amplified voltage.
The configuration shown in FIG. 25 is a modification of the configuration of FIG. 23. The point of change is that a reference voltage Vref is applied to the gate of the transistor M3 of the differential pair. The timing chart in controlling the respective switches of FIG. 25 is the same as that shown in FIG. 24.
Referring to FIG. 25, the switches SW1 and SW3 are turned on and the switch SW2 is turned off, during one data outputting time period t1. The input voltage Vin and the reference voltage Vref are supplied to the input pair of the differential pair (M3, M4), and an input voltage Vin is supplied common to the input pair of the differential pair (M5, M6). At this time, the output voltage Vout is a voltage corresponding to the reference voltage Vref added by the offset voltage Vf (Vref+Vf), and is stored in the capacitor C1.
Then, during the time period t2, the switches SW1, SW3 are turned off, whilst the switch SW2 is turned on. The input voltage Vin and the voltage stored in the capacitor C1 (Vref+Vf) are supplied to the input pair of the differential pair (M3, M4), whilst the input voltage Vin and the output voltage Vout are supplied to the input pair of the differential pair (M5, M6).
At this time, the input pair of the differential pair M3, M4 is supplied with the same voltage as that supplied during the time period t1 to maintain the differential pair (M5, M6) in the same state as that during the time period t1. Hence, the output voltage Vout during the time period t2 is stable at a voltage equal to the input voltage Vin. That is, with the configuration shown in FIG. 25, it is again possible to cancel out the output offset to amplify a voltage equal to the input voltage to output the so amplified voltage.
Meanwhile, the reference voltage Vref may be set to a mid value of the output voltage range of the amplifier circuit to reduce the potential variations of the output voltage Vout during the time period t1 to a value smaller than in the case of FIG. 23. This allows shortening the time period t1 and elongating the time period t2 of high accuracy driving.
[Patent Publication 1]
Japanese Patent Kokai Publication No. JP-P2001-292041A (FIG. 1)
[Patent Publication 2]
Japanese Patent Kokai Publication No. JP-P2003-168936A (FIG. 1)